In this article, we look at a quick way to automate your testbenches and find bugs in your code.
In this article, we put all the modules that we've designed in this series together and build a single unit of a CNN architecture.
This comprehensive guide aims to guide you in your search for the perfect FPGA development board.
An article showing beginners how they can generate a global reset signal at the initialization of the design without having to sacrifice a GPIO pin or a user button for the same
In this article we convert normal additions and multiplications in our design to fixed point representations. This will enable use to work with fractional numbers.
In this article we implement some common activation functions used in machine learning algorithms. This is a part of the series where we design a Convolutional Neural Network accelerator targeted towards FPGAs
In this article we design a module that can very efficiently perform Max Pooling and Average pooling of an input matrix in Verilog HDL. This will go into our Deep Learning accelerator as mentioned in the previous articles in the series.
There has been a lot of interest in the tech community lately to accelerate data intensive machine learning inference operations. This series of articles goes into a great detail in implementing an FPGA based accelerator in verilog HDL.
There has been a lot of interest in the tech community lately to accelerate data intensive artificial intelligence inference operations. This series of articles goes into a great detail in implementing an FPGA based AI accelerator in Verilog HDL.
In this article, we design a fully parameterized 2D convolution engine in Verilog HDL and verify its functionality with a golden model written in python.
A Shift registers is a very common design element in any digital design. This will be the only shift register you will ever need to write. The parameters in this code can be modified to create a shift register of any size and bit-width.