Creating automated testbenches for your digital designs using python and iverilog
In this article, we look at a quick way to automate your testbenches and find bugs in your code.
Digital Design4 posts
Putting it all together: The CNN accelerator
In this article, we put all the modules that we've designed in this series together and build a single unit of a CNN architecture.
Architecture Outline : Machine Learning Accelerator
There has been a lot of interest in the tech community lately to accelerate data intensive artificial intelligence inference operations. This series of articles goes into a great detail in implementing an FPGA based AI accelerator in Verilog HDL.
The convolution Engine
In this article, we design a fully parameterized 2D convolution engine in Verilog HDL and verify its functionality with a golden model written in python.